Efficient sequential circuits using critical race control

ABSTRACT

Methods and apparatus for controlling critical races in sequential circuits so that the there are no conflicts when two or more different data signals exists on shared circuit paths. This enables the design and implementation of sequential circuits having fewer gates than conventional circuit designs of equivalent function that translates into smaller area and power consumption. The control of the critical race is accomplished by adjusting the relative delay of the individual sections of one or more loops.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority under 35 U.S.C. Section 120 froma U.S. Provisional Patent Application serial No. 60/277,687 filed onMar. 21, 2001, which is incorporated herein by reference for allpurposes.

BACKGROUND OF THE INVENTION

[0002] 1. Technical Field of the Invention

[0003] This present invention relates to integrated circuit design, andmore particularly to synchronous and asynchronous sequential logiccircuits and controlling critical races therein.

[0004] 2. Background Art

[0005] Sequential logic circuits are heavily used in the implementationof very large scale integrated (VLSI) circuits. They appear asregisters, as memory elements, as counters, in pseudo-random codegenerators and everywhere that data has to be manipulated such as indigital filters, data paths and logic operations. Therefore theimprovement of such circuits such as a decrease in silicon area neededfor implementation and/or a decrease in power consumption, withoutimpairing other characteristics, is of prime importance to the VLSIindustry. The resulting characteristics of the improved circuits wouldincrease fabrication yield and/or increase the number of functions thatcan be implemented on the die.

[0006] Circuit size reduction also benefits conventional circuits thatare too large or consume too much power to be efficiently used in VLSIcircuits. For example, double edge-triggered D flip-flops (DETDFF)process data at both positive transition (low to high) and negativetransition (high to low) of the clock. Compared to positiveedge-triggered D flip-flop (PETDFF) which process data only at thepositive transition of the clock, the DETDFF doubles the rate of dataprocessing or, alternatively halves the clock rate thereby, eitherincreasing the data throughput or reducing power consumption in theclock circuit respectively. However the implementation of conventionalstatic DETDFF requires many gates and consumes too much silicon area tomake them an attractive design alternative in VLSI circuits.

[0007] Sequential logic circuits are characterized by their structurethat includes one or more feedback loops. The closed feedback loop“latches” or “stores” the present state of the circuit by closing thepath returning the value of the circuit to its input. In synchronoussequential circuits, the opening and closing of the loop is controlledby a transition (low to high or high to low) of the clock waveform. Thenew value appears at the output node after a “propagation delay” due tothe elements in the loop, and is held, or “memorized” by the loop untilthe signal to accept a new value appears.

[0008] The flip-flop is the basic synchronous sequential circuit.Flip-flops appear in various configurations or “types”, such as Dflip-flops, T flip-flops and J-K flip-flops where the D flip-flop is themost common. Flip-flops, of all three types, are usually configured asMaster-Slave flip-flops, i.e. a sequential structure using two latches,called master and slave respectively, in cascade. A latch is thesimplest sequential circuit containing a single feedback loop forstoring one bit of data.

[0009] In the case of a positive edge-triggered D flip-flop (PETDFF), apositive clock transition, or positive edge, determines the output ofthe flip-flop as that value present at its input just before the clocktransition. Thus for correct operation the input value has to bemaintained to a stable value just before and just after the clocktransition.

[0010] The correct operation of flip-flops is dependent on the timedelays internal to the feedback loops with respect to the external inputand clock waveforms. Excessive delay in the feedback loop can result infaulty operation of the flip-flop. In the conventional use of sequentiallogic circuits, the time delay of feedback loops is usually a smallfraction of the periods of input data and of clock waveforms and doesnot interfere with the correct operation of the circuit. Also in awell-designed sequential circuit, only one value is present at both endsof an open loop before the loop closes. At the appropriate closing timethe loop will then latch that value.

[0011] However when more than one value is input to a feedback loop, acritical race develops between the conflicting values. The final valuelatched in the circuit as result of the critical race depends on theinternal delay of the loop. The internal delay of a logic circuit loop,although generally small with respect to the periods of data and clock,is not well defined, as this delay is dependent on the parasiticelements in the loop. These parasitic elements are due to the non-linearinput and output capacitances of the transistors, capacitive couplingwith other elements, interconnection and load capacitances and finiteresistance and inductance of wiring and switching transistors when beingactivated (in the “on” state).

[0012] One way to reduce the number of components in a master-slaveflip-flop (M/S FF), and therefore reducing the required silicon areaneeded to implement it, consists of sharing a gate between the masterlatch and the slave latch. This eliminates one gate and its optionalassociated reset line. However sharing of the gate results in couplingbetween the feedback loops of the master and slave latches. Thiscoupling between loops introduces critical races as the final state ofthe shared loop depends upon the value of which of the two latches willprevail and be the one to be latched. This critical race time intervalis relatively small compared to the periods of clock and data, and isdependent upon the parasitic capacitances and resistances present in thecoupled loop. The precise values of parasitic capacitances andresistances are unknown as they depend on the fabrication process. Thus,removing gates in the manner just described introduces critical racesinto the circuit, the final state of which is unknown.

[0013] This method, which introduces critical races, is therefore notpractical or commercially viable. Accordingly, design practices forsequential logic circuits teach away from using critical race conditionsin a circuit as this is assumed to create conditions that would make thecircuit fail and/or generate unpredictable outcomes. Therefore presentflip-flop configurations include additional circuitry to guarantee theabsence of critical race conditions.

[0014] An additional way to avoid critical races is to have additionalcomponents to delay certain paths or to provide additional latching.However, as discussed herein, additional circuits increase powerconsumption and circuit area space.

[0015] In asynchronous sequential circuits critical races are also aproblem, as no clock synchronization is used to close or open thefeedback loop. In these circuits, as the feedback loop opens and closesunder control of external signals unrelated to each other, more oftenthan not more than one value is available instantaneously in the loopand critical races are often present.

[0016] Numerous approaches, such as unusual clocking and circuitryarrangements, have been used to eliminate race conditions and reducecircuit size. One example, U.S. Pat. No. 5,072,132, teaches a means ofreducing circuit size by the use of a pulse generator coupled to theclock input of the latch. According to this design, a pulse generatorproduces sliver pulses correlating to the propagation delay through thelatch of the state device circuits and thus purportedly enables a singlelatch to act as a flip-flop without racing. Alternatively, U.S. Pat. No.4,841,168 teaches increasing circuit density by reducing gates, whileavoiding racing. This is obtained by sharing a data gate between masterand slave latches such that a latch gate of the master latch is sharedby the slave latch as a data gate. Additionally, the clock signal isaltered by changing the signal transmission speed of the clock on theslave side of the gate and adding control signals to the clock driver.

[0017] Additional background information on critical races can be foundin “Fundamentals of Logic Design”, by Charles H. Roth, Jr., WestPublishing Company, 1992, Ch. 23, p. 602-603 and Ch. 25, p.629.Operation of a static double edge-triggered flip-flop is detailed in thepaper: “High-performance two-phase micropipeline building blocks: doubleedge triggered latches and burst mode select and toggle circuits” byYun, K. Y., Beerel, P. A. and Arceo, J. in IEE Proc., Circuits, Devices,Syst., 1996, 143,(5),pp.282-288.

[0018] As can be seen, attempts to reduce circuit size have not onlybeen frustrated by the risk of critical races, but the solutions to theproblem of critical races generally involves complication of thecircuit's clocking arrangement or the addition of other circuitry toenable the device. What is needed therefore, is a method and apparatusfor controlling critical races in sequential circuits that facilitatesimplementation of circuits with fewer gates and on smaller silicon areawithout the need of adding components or implementing compensatoryclocking schemes.

SUMMARY OF THE INVENTION

[0019] The invention is devised in the light of the problems of theprior art described herein. Accordingly it is a general object of thepresent invention to provide a novel and useful technique that can solvethe problems described herein.

[0020] In addition, the critical race control techniques of the presentinvention give rise to configurations of sequential integrated circuitswith less area and lower power dissipation than conventionalimplementations. The techniques of the present invention also simplifiesthe design of asynchronous circuits by solving the problem of criticalraces.

[0021] Critical race control reduces the number of logic gates necessaryto implement the circuit by sharing some gates and circuit paths amongdata latches. This technique achieves a corresponding reduction inrequired silicon area while controlling the result of critical racesthus enabling the circuit to function properly. In addition, theresulting sequential circuits, as disclosed herein, consume less powerin some applications.

[0022] Methods and apparatus for implementing critical race control insequential circuits are disclosed herein. Critical race control meetsthe needs identified herein by adjusting the relative delay of theindividual sections of the shared feedback loop with respect to oneanother through adjustment of the delay of the transmission gate in eachsection.

[0023] The effect of this regulation is the control of critical races byensuring that only data from the desired input is allowed to determine agiven gate's output when two or more different data exists on a sharedcircuit paths. This enables the design and implementation of sequentialcircuits having fewer gates than found in conventional circuit designsof equivalent function.

[0024] Critical race control may be used in a wide range ofapplications, particularly those involving static sequential circuits.As described herein, critical race control may be readily embodied inthe commonly used master-slave edge-triggered flip-flop circuits.Examples of embodiments include a D flip-flop, a static shift registerand a static double-edged -triggered D flip-flop circuit forapplications wherein data and clock rates are equivalent. In addition,an embodiment of an integrated shift right-shift left register withsmaller number of gates than the conventional implementation of thatfunction is also included.

[0025] Critical race control (CRC) can be successfully applied tofacilitate the design of asynchronous circuits by eliminating theconcern for critical races, therefore obtaining circuits with a lowernumber of gates as compared to present implementation methods. Anexample is presented using CRC for the implementation of an asynchronouscircuit containing critical races that cannot be implemented withpresent methods. These embodiments exemplify the wide range of use andflexibility of this new technique.

[0026] The effective delay in a transmission path section, can bechanged by altering its time constant through modification of itsresistance, and/or its capacitance or by varying the current andvoltages charging and discharging the various elements in the path orstill, by changing the threshold voltages of the logic gates in theloop. In practice a combination of some or all of the above methods,including varying power supplies, clock rates and other parameters maybe used. In VLSI circuits the designer has almost no control on theparasitic capacitances except for the desire to minimize them, thereforeit is easier to modify the resistances in the paths. Fortunately, theresistance of the transmission gate can be easily and robustly regulatedby adjusting the size of its constituent transistors during design.

[0027] In large VLSI dies there are variations in transistors parametersdue to the non-uniformity of the VLSI fabrication process over the sizeof the die. Changes in local environmental and electrical conditions onlarge dies, such as high local temperature (“hot spots”) and localsupply voltage variations, will also induce variations in the operatingconditions of individual transistors, and therefore on circuits, atdifferent locations on the die. Therefore circuits relying on absoluterelations between parameters of transistors for correct operation arenot robust and cannot operate over a wide range of environmental andprocess fabrication parameters. Critical race control, as describedherein relies on the ratio of resistance of only two transmission gatesthat are in very close physical proximity to one another as they are inthe same loop of the same flip-flop. Under this condition of closeproximity, both the transistor parameters and variations inenvironmental and electrical conditions will, for all practicalpurposes, be identical in both transmission gates.

[0028] Accordingly by establishing a desired ratio between theresistances of the proximate transmission gates, it is possible toreliably control the delay in various sections of the loop and controlthe outcome of a critical race.

[0029] This technique can be used with all other master/slaveimplementations. For example, U.S. Pat. No. 5,497,114 describes amaster-slave flip-flop that uses single pass transistors to replace theconventional transmission gate used in a flip-flop. The critical racecontrol can be used on that type of flip-flop too to reduce the numberof gates.

[0030] An object of the invention is a method for producing efficientintegrated sequential circuits, comprising the steps of providing atleast one data input signal and at least one clock signal, and designingone or more circuit loops each having a plurality of sections and two ormore switches wherein the switches in the loops separate between thesections. Another step is controlling a critical race of the loops byadjusting a relative delay of the sections.

[0031] An additional object is the method for producing efficientintegrated sequential circuits, wherein the switches are one or moretransistors and the relative delay is regulated by adjusting transistordimensions, such as length and width. In another embodiment the relativedelay is regulated by adjusting a resistance or capacitance of thetransistors. Alternatively, the switches are transmission gates and therelative delay is regulated by adjusting a resistance/capacitance (RC)time constant of the transmission gates.

[0032] A further object is the method for producing efficient integratedsequential circuits, wherein the relative delay is adjustable byexternal parameters. Although not inclusive, the external parametersinclude clock frequencies, supply voltages (Vdd), ground supplies (Vss),bias voltages, and temperature. A further embodiment relates to therelative delay that is dynamically controllable by the externalparameters. Such dynamic control allows for changing the delay andaltering the critical race conditions.

[0033] Along this same line, another object is the method for producingefficient integrated sequential circuits, wherein the switches aretransmission gates and the relative delay is regulated by adjusting aset of fabrication process parameters directly or indirectly effectingthe transmission gates. Such fabrications include doping concentration,implant concentration, threshold voltage, polysilicon dimensions,polysilicon composition, substrate dimensions, diffusion dimensions,metal dimensions and oxide dimensions. The direct effects would beapplicable based upon changes to the transmission gates itself, whilethe indirect effects would effect other logic circuits that areinterconnected to the transmission gates.

[0034] And an additional object is the method for producing efficientintegrated sequential circuits, wherein the switches are transistors andfurther comprising the step of locating the transistors in closeproximity. Such proximity avoids differences in transistors and morecertainty when regulating the relative delay.

[0035] An object includes the method for producing efficient integratedsequential circuits, wherein the relative delay is a first propagationdelay in a first section as compared to a second propagation delay in asecond section, wherein the first and second section are within the sameloop or coupled loops.

[0036] In addition, the method for producing efficient integratedsequential circuits, wherein said relative delay is introduced byresistors within the section. Another object further comprising logiccircuits in the sections, and wherein the logic circuits provide therelative delay. Any of the components in the sections can be used toestablish the proper relative delay.

[0037] And yet another object is the method for producing efficientintegrated sequential circuits, wherein integrated circuits are from thegroup comprising single edge-triggered flip-flops, double edge-triggeredflip-flops, D flip-flops, T flip-flops, J-K flip-flops, binary memoryelements and S-R flip-flops. Also including efficient integratedsequential circuits, wherein integrated circuits are from the groupcomprising flip-flops-based registers, shift registers, counters, pseudorandom generators, memory devices.

[0038] An object also includes the method for producing efficientintegrated sequential circuits, wherein a data flow is in more than twodirections, such as forward and reverse.

[0039] An object of the invention is a sequential circuit comprising adata input, a data output, a loop with a plurality of sections coupledto the data input and the data output. There is a means for controllinga critical race by adjusting a relative time delay between the pluralityof sections.

[0040] Additionally, the sequential circuit, wherein the means forcontrolling is changing a ratio of a resistance/capacitance (RC) timeconstant between the sections. Also, further comprising two or moretransmission gates and a plurality of logic devices connected in theloop and wherein the relative time delay is a difference in propagationtime delay between the sections of the loop. Accordingly, one of themeans for controlling is a ratio of resistance of the sections of theloop. The relative delay is also established where the ratio ofresistance is between the transmission gates of the sections. And,wherein the relative delay is between the logic devices of the sections.Furthermore, wherein the relative time difference is changed byadjusting a size of the transmission gates size of capacitance of thesections.

[0041] An object of the invention is a sequential circuit comprising adata input, a first loop with a plurality of first loop sections,wherein the first loop is coupled to the data input, and a second loopwith a plurality of second loop sections, wherein the second loop iscoupled to the first loop. An output node is coupled to the first andsecond loop such that the output is derived from either loop. There is ameans for controlling a critical race between the first loop sectionsand between the second loop sections by adjusting a relative time delaybetween the first loop sections and between the second loop sections.

[0042] Yet an additional object is the sequential circuit, wherein themeans for controlling is changing a ratio of a resistance/capacitance(RC) time constant between the first loop sections and the second loopsections. The sequential circuit, further comprising two or moretransmission gates and a plurality of logic devices connected in thefirst loop and comprising two or more transmission gates and a pluralityof logic devices connected in the second loop, and wherein the relativetime delay is a difference in propagation time delay between thesections of the first loop and the sections of the second loop. And, themeans for controlling is a ratio of resistance of the sections of thefirst loop and the sections of the second loop. Or, the ratio ofresistance is between the transmission gates of the sections of thefirst loop and the transmission gates of the sections of the secondloop, either individually or coupled loops.

[0043] Still other objects and advantages of the present invention willbecome readily apparent to those skilled in this art from the followingdetailed description, wherein we have shown and described only apreferred embodiment of the invention, simply by way of illustration ofthe best mode contemplated by us on carrying out our invention. As willbe realized, the invention is capable of other and differentembodiments, and its several details are capable of modifications invarious obvious respects, all without departing from the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The present invention will be readily understood by the followingdetailed description in conjunction with the accompanying drawings,wherein like reference numerals designate like structural elements, andin which:

[0045]FIG. 1 shows a prior art conventional positive edge-triggeredflip-flop with reset in a master-slave configuration.

[0046]FIG. 2 shows a preferred embodiment of Critical Race Control,wherein a typical positive edge-triggered master-slave D flip-flop hasbeen modified to comprise fewer gates. Control of the critical racecondition occurring due to the shared circuit path between latches, isobtained by adjusting the ratio between the resistances of transmissiongates TG2 and TG3 through control of the size of their transistors.

[0047]FIG. 3a represents the initial state of the new flip-flop when thecurrent value is 0 and a new data of value VDD is present at the input.

[0048]FIG. 3b represents the state of the circuit in FIG. 3a at the timeof the clock transition from a low level to a high level.

[0049]FIG. 4a represents the equivalent electrical circuit of the logiccircuit shown in FIG. 3b, including the relevant parasitic elements.

[0050]FIG. 4b represents the equivalent electrical circuit of the logiccircuit in FIG. 3b during the settling time of the shared loop, at thetime node Q transitions from a low to a high value.

[0051]FIG. 5a shows an embodiment of a static shift register comprisingfewer gates and shared circuit paths wherein critical races arecontrolled by adjusting the ratio of the resistances of the transmissiongates.

[0052]FIG. 5b compares output waveforms from two 3 stage shiftregisters: one shift register implemented with conventional D flip-flopsas shown in FIG. 1 and the second implemented with the new structure asshown in FIG. 5. The two sets of waveforms are undistinguishabledemonstrating the speed equivalence of the two structures.

[0053]FIG. 5c compares the average power dissipation during a clockperiod of one stage of the shift registers. The new structuredemonstrates, with this particular design, about 23% lower powerdissipation.

[0054]FIG. 6 shows an embodiment of an integrated right-shift left-shiftregister wherein critical races and direction of data flow arecontrolled by the ratio of the resistance of the transmission gates asindicated. This circuit does not require an additional clock signal asneeded in conventional implementation of this function. Control of theleft or right direction of data flow is done using the control line BW.To obtain left (backward) direction of data propagation the transmissiongate resistance ratio is switched to a different value than that chosenfor the forward direction of data propagation.

[0055]FIG. 7 shows an embodiment of the new D flip-flop using singlepass transistor instead of transmission gates and a single-phase clock

[0056]FIG. 8 shows a conventional static double-edged triggeredflip-flop circuit.

[0057]FIG. 9a shows an embodiment of a static double-edge triggeredflip-flop comprising shared circuit paths wherein critical races arecontrolled by adjusting the ratio of the resistances of the transmissiongates.

[0058]FIG. 9b is a graphical presentation of the outputs of the shiftregister using double-edge flip-flops.

[0059]FIG. 10a shows the implementation of a set-reset latch (S-R latch)using NOR gates and requiring rising pulses to set and reset the latch.

[0060]FIG. 10b shows the implementation of the same S-R latch but usingNAND gates and requiring negative going pulses to set and reset thelatch.

[0061]FIG. 11 shows an asynchronous circuit, composed of combinationalcircuits and S-R latches, that is subject to critical races.

[0062]FIG. 12 shows the circuit of FIG. 11 redrawn to reveal the loopstretching from the output of the second S-R latch back to the NAND gatecontrolling the set node of the first latch. By adjusting the ratio ofthe delays between the two parts of the circuit formed by each latch andits logic gates controlling the set and reset nodes, it is possible tocontrol the result of the critical races.

[0063]FIG. 13 shows the implementation of NAND and NOR logic gates withtransmission gates. These gates, or a modified version of them, can beused for implementing the combinational circuit controlling the set andreset nodes of the latches. Use of such gates allows for the adjustmentof the delays of the individual sections of the loop.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0064] The methods and embodiments of critical race control disclosedherein enable implementations of sequential circuits with fewer logicgates and functionality equal to that of circuits constructed accordingto existing methods and configurations. In some applications, reducedpower consumption is also obtained.

[0065] Critical race control, as disclosed herein, is achieved byincreasing the delay of one section of the shared feedback loop withrespect to the other section. The time constant is controlled byadjusting the resistance of the constituent transistors in thetransmission gate in each section of the feedback loop and adjusting thecurrent charging and discharging capabilities of the logic gates.Increasing the delay of one transmission gate relative to the otherensures that the final state of the critical race is well defined.Controlling critical race conditions according to the present inventionobviates the need for circuits with additional circuitry and specialclock waveforms.

[0066] One preferred embodiment of critical race control is illustratedby comparing a typical edge-triggered master-slave D flip-flop circuit[FIG. 1] to a comparable circuit constructed according to critical racecontrol [FIG. 2]. Other types of flip-flops use similar staticsequential circuit architecture with different external gates to obtaindifferent functionality. Accordingly, critical race control may also beapplied to T- and J-K master-slave flip-flop circuit designs, becausethe internal architecture of the sequential circuit is the same.Examples of some other applicable embodiments are disclosed in FIGS. 5,6, 7 and 9 described herein. Critical race control can also be appliedto other sequential circuits as well as to asynchronous sequentialcircuits as shown in FIGS. 11 and 12.

[0067] The circuits analyzed and demonstrated in this present inventionare static or pseudo-static where the latter indicates that thesecircuits remain in their state as long as the clocks present adequatevoltage levels. From here on both types of circuits will be calledstatic.

[0068] A typical implementation of a positive edge-triggeredmaster-slave D flip-flop is shown in FIG. 1. The master latch compriseslogic gates G1 and G2, and transmission gates TG1 and TG2 while theslave latch comprises logic gates G3 and G4, and transmission gates TG3and TG4. Gates G1 and G4 are inverters, gates G2 and G3 are NOR gateswhere one of the inputs to the NOR gate is used to set asynchronouslythe initial state of the flip-flop.

[0069] Transmission gates TG1, TG2, TG3, and TG4 act as switches inseries with the signal and are controlled by the amplitude of the clocksignal. Each transmission gates consists of a pair of p-type and n-typeFET transistors such that the transmission gate toggles between open(on) and closed (off) as a function of a high or low clock signalrespectively. When a transmission gate is “open” or “on,” it functionssimilarly to a closed switch and signal passes through it. When atransmission gate is “closed” or “off,” it functions similarly to anopen switch and signal does not pass through it.

[0070] Referring to FIG. 1, when the clock signal (CLK) is low,transmission gates TG1 and TG4 are open and transmission gates TG2 andTG3 are closed. Input data at node D propagates through transmissiongates TG1 and logic gates G1 and G2 and is stored on the inputcapacitors of gates G1 and G2. Note that the input data cannot latch inthe master latch due to TG2 being closed. Nor can the data propagate tothe slave latch due to TG3 being closed. Accordingly, the presentoutput, Q_(old) is determined by data already latched in the slave latchthrough G4, TG4, and back through G3.

[0071] When the clock signal goes high, transmission gate TG1 closeswhile transmission gate TG2 opens. The data appearing in the masterlatch at the input of G1 and G2 is now latched when transmission gateTG2 closes the loop. At the same time, transmission gate TG4 closesopening the slave loop while transmission gate TG3 opens and the dataavailable in the master latch at output of G1 propagates through opentransmission gate TG3 to G3's input. The new output, Q_(new), nowappears at the output of gate G3.

[0072] When the clock signal again goes low, transmission gates TG2 andTG3 close and gates TG1 and TG4 open. G3's output data is latched in theslave loop through G4, TG4, and G3, so output Q_(new) remains the samewhile the slave latch is disconnected from the master latch by closedtransmission gate TG3. Meanwhile, transmission gate TG1 is open, suchthat G1 and G2 may again receive new data propagating through TG1.

[0073] It will be noted that in each loop, whether in the master latchor in the slave latch, there is only one transmission gate that closesor opens the circuit loop for a given clock transition. This is TG2 forthe master latch and TG3 for the slave latch. When the transmission gateopens, the data present at the input side and output side of thetransmission gate in the loop is the same, due to the two logicinversions in each loop. Thus when the loop is closed, no transientvoltages are produced. With a flip-flop designed and operating in thismanner, the master and slave latches function discretely from each otherto alternately store data in accordance with the clock cycles and theopenings and closings of the transmission gates. Thus, as the clocksignal rises and falls, each bit of data steps from the master latch tothe slave latch with no possibility of conflicting data on any path orat any gate.

[0074]FIG. 2 illustrates an embodiment of a positive edge-triggered Dflip-flop circuit constructed according to critical race control (CRC).In contrast to the flip-flop circuit shown in FIG. 1, it will be notedthat logic gate G2 has been deleted. G3 now performs the invertingfunction of the deleted gate G2. The master latch in FIG. 2 nowcomprises TG1, G1, TG3, G3, and TG2. Transmission gate TG2 is marked bya star signifying a longer propagation delay, to distinguish it fromtransmission gate TG3 as will be explained below. The flip-flop circuitretains the original slave latch TG3, G3, G4, TG4, but the master andslave loops now share gate G3. It should be noted that there are now twoswitches, TG2 and TG3, in the shared master loop, opening and closingthe loop simultaneously. The two switches divide the loop into twodistinct sections. This circuit configuration, in which the loop iscomposed of two sections, introduces conflicting data when the value atinput node D differs from the present value at output node Q.

[0075] This is because each section of the loop maintains a differentvalue when the loop is open (gates TG2 and TG3 closed, gates TG1 and TG4open). Under these conditions the data at each terminal of transmissiongate TG2 will be different. Similarly the data at each terminal oftransmission gate TG3 will also be different as the new data propagatingfrom node D to the output of G1 will differ from the data propagatingfrom node Q to the output of G4 and TG4. This state is stable becausetransmission gates TG2 and TG3 are presently closed.

[0076] However at the moment the loop closes (gates TG2 and TG3 open,gates TG1 and TG4 closed) the presence of two different values at theopposite ends of transmission gates TG2 and TG3 acting as resistancesresults in an unstable state. This state is unstable because thephysical laws force the logic data to be the same at both ends of aconducting transmission gate. Due to this unstable state there will be abrief transient period at the end of which the voltages will reachstable values. These final values depend on a race between which of thevalues of Q or of D will prevail in the loop. The final state of thisrace depends on the threshold values of the gates, on the charging anddischarging currents and on the parasitic elements in the loop. Thevalue that will be latched in the loop depends therefore on the outcomeof that race and is therefore critical.

[0077] This is unlike the situation of the circuit in FIG. 1, where theloop in each latch, whether master or slave, is open or closed by onlyone switch thus ensuring the same values at each end of the loop priorto closing it.

[0078] For correct operation of the circuit in FIG. 2, the new value ofD must prevail. For this to happen it is necessary that, when gates TG2and TG3 open, the data appearing at the input node of GI modifies node Qand latches its value in the loop before the old value Q_(old) togglesG1 thereby modifying the input value. This condition can be assured bycontrolling separately the delays in each section of the shared loop andis the essence of the critical race control invention.

[0079] The critical race control invention can be explained bydemonstrating its operation on the typical circuit in FIG. 2. We startat time t=t₀ with the circuit in the initial conditions shown in FIG.3a. D is the input node of transmission gate TG1, D_(1tch) is the outputnode of TG1 and the input node of inverter G1, and D_(b) is the outputnode of G1 and input node of TG3. G_(3in) is the output node of TG3 andthe input node of G3. Node Q is G3's output. In this state the clockvoltage (not shown) is low, causing transmission gates TG1 and TG4 to beopen (on) and transmission gates TG2 and TG3 to be closed (off). Theoutput Q of the flip-flop, is low (0) while complementary output Q_(b)and node G_(3in) are both high.

[0080] At some time a signal of value VDD is received at input node D.Accordingly, the voltage on node D_(1tch) is V_(D1tch)=VDD and thevoltage on node D_(b) is V_(Db)=0. As no change in the clock has yetoccurred all transmission gates retain their present states, the slavelatch loop comprising G3, G4, and TG4 remains latched, and nodes G_(3in)and Q retain their latched values, that is: VG_(3in)=VDD and V_(Q)=0.The circuit remains in this state as long as the clock value is low.

[0081]FIG. 3b shows the state of the circuit at time t=t₀₊, which is theinstant the clock signal changes from a low to a high value. This causesthe four transmission gates to rapidly switch to their complementarystates. Gates TG1 and TG4 are now closed (off), and gates TG2 and TG3are now open (on). At the instant t=t₀₊, the voltages on the relevantnodes have not yet changed, so transmission gates TG2 and TG3 are nowconnecting between nodes having different voltages. On the G1 side ofTG3, V_(Db)=0 while on the G3 side of TG3, VG_(3in)=VDD. On the G3 sideof TG2, V_(Q)=0. while on the G1 side of TG2, V_(D1tch)=VDD. This is anunstable state as the voltages on each side of a transmission gate arerequired to be of the same digital value. Therefore the voltages in theclosed loop are rapidly changing to reach final, stable values.

[0082] The closed loop can exist in two stable states. In the firststable state nodes Q and D_(1tch), have a value 0 and nodes D_(b) andG_(3i) have a value of VDD. In the second stable state nodes Q andD_(1tch), have a value of VDD and nodes D_(b) and G_(3in) have a valueof 0. Which of the two stable states will be the final one is determinedby the values of the parasitic elements in each section of the loop.Therefore, a critical race between the two values occurs during the timethat the voltages are reaching a stable value.

[0083] The description of the technique enabling reliable control of theoutcome of the critical races in sequential circuits is one of thesubjects of the present invention. By adjusting the propagation delay ofone section of the loop in relation to the propagation delay of theother section, it is possible to exercise reliable control over thecritical race condition. Specifically, referring to FIG. 3b,transmission gates TG2 and TG3 divide the loop into two sections. Therace occurring at the time the transmission gates TG2 and TG3 areclosed, that is at time t=t₀₊, is between the value at node D_(b) andthe value at node 0. If the value at node D_(b) succeeds in changing thevalue at node Q before the present value of node Q i.e. Q_(old),succeeds in changing the value of node D_(b), then the circuit willoperate correctly. Otherwise the master-slave flip-flop shown in FIG. 2will retain the old value.

[0084] This critical race in the loop is controlled by increasing thepropagation delay in the path from node Q to node D_(1tch) as comparedto the propagation delay in the path from node D_(b) to node Q. Thisensures that node Q will flip to its new value Q_(new), before the oldvalue Q_(old), will be able to modify the value at node D_(b). Thus thenew value at node Q will always be determined by the incoming new datastored at node D_(1tch).

[0085] Control of the propagation delay in a section of the loop can berealized in many ways. Voltage supplies, clock rates and other externalparameters, such as temperature (identical loop sections at differenttemperatures have different propagation delays) can be modified.Internally, the current source and sink capabilities of the logic gatescharging and discharging the devices in the appropriate circuitsections, their threshold voltages and their parasitic elements can beadjusted. The propagation delay can also be controlled by modifying thevalues of the capacitances and/or of the resistances of the devices inthat section. From a practical aspect however, control of the timeconstant of each section of the loop is readily done in CMOS technologyby using a circuit design style employing transmission gates andadjusting the resistance of the transmission gates. This is easily andcommonly accomplished by modifying the width, W, and the length, L, ofthe gates of the transistors in the transmission gates. Modifying thevalues of other parasitic elements, such as capacitances, is moredifficult as the capacitances are in parallel to the nodes of interestand cause additional loading which reduce speed and increase powerconsumption of the circuits.

[0086] It is worthwhile to note that critical race control describedherein is very robust as it depends on the ratio of the time constantsof two separate parts of the same feedback loop, and not on theirabsolute value. The close proximity of the two parts of the loopminimizes the small but ever-present variations between transistors dueto technical limitations of the fabrication processes, such asnon-uniformity of the oxide thickness over the die, and variancesinduced by local environmental effects, such as thermal differences andsupply voltages. This technique therefore guarantees that bothtransistors behave identically over large variations in the operatingconditions of the circuit and that it is possible to specify andmaintain an established resistance differential between TG3 and TG2across a wide range of temperature, supply voltage, and fabricationparameters.

[0087] The inventive technique of critical race control requires thatthe designer take into account the parasitic elements that, throughtheir time constant, decide the critical race outcome. To account forthese elements, the circuit in FIG. 3b is redrawn to model its parasiticelectrical components, as shown in FIG. 4a. In that figure thenon-linear and time-varying parasitic capacitances and transmission gateresistances are characterized by constant parameters. Inverter G3 modelsthe electrical equivalent of NOR gate G3. Capacitor C_(L) represents thesum of: load capacitances, gate G3 output capacitance, gate G4 inputcapacitance, and other parasitic capacitors at node Q. Similarly,capacitors C_(IN) and C_(G3) model the sums of input and all parasiticcapacitors at nodes D_(1tch) and G_(3in), respectively. Resistors R₂ andR₃ model the resistances of transmission gates TG2 and TG, respectively.Inverters G1 and G3 are assumed to be ideal, with threshold voltages ofV_(thG1) and V_(thG3) respectively.

[0088] For correct operation of the circuit, the change in voltageoccurring at node D_(1tch) of the loop during the settling period mustbe limited to a magnitude that keeps the output of gate G1 constantwhile the circuit reaches its stable state. Thus, during the settlingprocess, the instantaneous value of the voltage on node D_(1tch) cannotcross the voltage threshold V_(thG1), This constraint will determine therequired ratio of the time constants of the transmission gates. Our goalis to derive the ratio of resistance between transmission gates TG2 andTG3 for correct operation of the circuit.

[0089] The following equations help describe the behavior of the circuitunder critical race control. These equations and the models used areapproximations. Still, they clearly show the main approach to controlcritical races. For detailed design of the final circuit within aspecific technology and under well-defined environmental conditions,computer aided software is necessary.

[0090] The derivation follows the assumption shown in FIG. 3a with apresent state: Q=0 and an input value of VDD. The same set of equationsis obtained in the complementary case when Q=1 and an input value of 0.

[0091] The minimum voltage (maximum for the case of Q=1 and D=0) allowedon node D_(1tch) for correct circuit operation is computed by firstfinding the time of its occurrence, then computing the correspondingvoltage at that time. The analysis in FIG. 4a begins at time t=t₀₊, whenthe clock voltage switches from LOW to HIGH and transmission gates TG2and TG3 toggle to their “ON” state. The initial conditions at that timeare shown in FIG. 4a: V_(D1tch)=VDD, V_(Db)=0, V_(G3in)=VDD and V_(Q)=0.Due to the conflicting values appearing at the terminals of TG3, theinitial voltage of VDD on capacitor C_(G3) will decrease. This voltagewill decay through R₃ from its initial value of VDD according to thewell-known exponential voltage decay law:${V_{CG3}(t)} = {{VDD}\quad ^{- \frac{t}{R_{3}C_{G3}}}}$

[0092] Gate G3 will toggle and provide an output voltage of VDD whenV_(CG3)(t) drops below the threshold voltage V_(thG3). The switchingtime of the idealized G3 is assumed negligible. The elapsed time forV_(CG3) (t) to reach the threshold voltage V_(thG3) is labeled t₁, andcan be expressed as (equation 1): $\begin{matrix}{t_{1} = {R_{3}C_{G3in}\ln \frac{VDD}{V_{thG3}}}} & (1)\end{matrix}$

[0093] During the same time period, from t=t₀₊ to t=t₁, the voltage oncapacitor C_(IN) discharges through R₂ according to:${V_{CIN}(t)} = {{V_{CIN}\left( 0^{+} \right)}^{- \frac{t}{R_{2}C_{IN}}}}$

[0094] Using the expression for t₁ just found, the voltage on C_(IN) attime t₁ with initial value V_(CIN)(0⁺)=VDD, can then be expressed as(equation 2): $\begin{matrix}{{V_{CIN}\left( t_{1} \right)} = {{V_{Dltch}\left( t_{1} \right)} = {{VDD}\quad ^{- \frac{R_{3}C_{G3}\ln \frac{VDD}{V_{thG3}}}{R_{2}C_{IN}}}}}} & (2)\end{matrix}$

[0095] After G3 toggles node Q has value VDD and the state of thecircuit is as shown in FIG. 4b. Gate G3 is modeled as a currentgenerator supplying a current I_(Q). This current charges capacitorC_(IN) so as to keep V_(CIN) above the threshold voltage V_(thG1) ofinverter G1. For the time period after G₃ toggles, i.e. for t≧t₁, thevoltage on node V_(CIN) is given by the superposition of the voltagesdue to the charging current I_(Q) and the discharging of capacitorC_(IN) from its initial value V_(D1tch)(t₁) (equation 3):$\begin{matrix}{{{V_{CIN}(t)} = {{\frac{I_{Q}}{C_{IN} + C_{L}}\left\lbrack {t + {R_{2}{C^{\prime}\left( {^{- \frac{t}{R_{2}C^{\prime}}} - 1} \right)}}} \right\rbrack} + {{V_{Dltch}\left( t_{1} \right)}\left\lbrack \frac{C_{IN} + {C_{L}^{- \frac{t}{R_{2}C^{\prime}}}}}{C_{IN} + C_{L}} \right\rbrack}}}{{{where}\quad C^{\prime}} = \frac{C_{IN}C_{L}}{C_{IN} + C_{L}}}} & (3)\end{matrix}$

[0096] The voltage on capacitor C_(IN) reaches its minimum when thecharging rate equals the discharge rate. This condition is equivalent tothe first derivative of V_(CIN)(t) being equal to 0. Thus to find thistime labeled t₂:$\frac{\partial{V_{CIN}(t)}}{\partial t} = {{{\frac{I_{Q}}{C_{IN} + C_{L}}\left\lbrack {1 - ^{- \frac{t}{R_{2}C^{\prime}}}} \right\rbrack} - {{V_{Dltch}\left( t_{1} \right)}\frac{C_{L}^{- \frac{t}{R_{2}C^{\prime}}}}{\left( {C_{IN} + C_{L}} \right)R_{2}C^{\prime}}}} = 0}$

[0097] which results in:$t_{2} = {R_{2}C^{\prime}{\ln \left\lbrack {1 + {\left( {1 + \frac{C_{L}}{C_{IN}}} \right)\frac{V_{Dltch}\left( t_{1} \right)}{I_{Q}R_{2}}}} \right\rbrack}}$

[0098] The minimum value of V_(CIN) must remain above the thresholdV_(thG1) in order for the circuit to operate correctly. This minimum cannow be obtained by inserting t=t₂ in eq. (3). The minimum voltage isthen obtained as: $\begin{matrix}{{V_{CIN}\left( t_{2} \right)} = {{\frac{C_{IN}}{C_{IN} + C_{L}}\left\{ {{I_{Q}R_{2}\frac{C_{L}}{C_{IN} + C_{L}}{\ln \left\lbrack {1 + {\left( {\frac{C_{L}}{C_{IN}} + 1} \right)\frac{V_{Dltch}\left( t_{1} \right)}{I_{Q}R_{2}}}} \right\rbrack}} + {V_{Dltch}\left( t_{1} \right)}} \right\}} > V_{thG1}}} & (4)\end{matrix}$

[0099] The ratio $\frac{R_{3}}{R_{2}}$

[0100] can now be found by inserting the value of V_(D1tch)(t₁) in eq.(4).

[0101] The result is a transcendental equation that generally has to beresolved using computer software. However a coarse indication of theratio can be obtained by using the following approximations: Looking atequation (4) and assuming that I_(Q)R₂>>V_(D1tch)(t₁) then thelogarithmic term in the braces is much smaller than V_(D1tch)(t₁) . Weare then left with the following simplified equation $\begin{matrix}{{V_{CIN}\left( t_{2} \right)} = {{\frac{C_{IN}}{C_{IN} + C_{L}}\left\{ {V_{Dltch}\left( t_{1} \right)} \right\}} > V_{thG1}}} & (5)\end{matrix}$

[0102] Inserting the value of V_(D1tch)(t₁) from eq. (2) we obtain$\begin{matrix}{{\frac{C_{IN}}{C_{IN} + C_{L}}V\quad D\quad D\quad ^{{- \frac{R_{3}}{R_{2}}}\frac{C_{G3}}{C_{IN}}\ln \frac{VDD}{V_{thG3}}}} > V_{thG1}} & (6)\end{matrix}$

[0103] From eq. (6) we obtain the ratio $\frac{R_{3}}{R_{2}}$

[0104] as: $\begin{matrix}{\frac{R_{3}}{R_{2}} < {\left( \frac{C_{IN}}{C_{G3}} \right)\frac{\ln\left\lbrack \frac{VDD}{V_{thG1}\left( {1 + \frac{C_{L}}{C_{IN}}} \right)} \right\rbrack}{\ln \left( \frac{VDD}{V_{thG3}} \right)}}} & (7)\end{matrix}$

[0105] Assuming all capacitances and threshold voltages to be equal,then with a threshold voltage V_(th)=⅓VDD, we obtain$\frac{R_{3}}{R_{2}} < {0.37.}$

[0106] This result clearly indicates the need for TG3 to have a lowerpropagation delay than that of TG2 for correct operation of the circuit.

[0107] In practice, the ratio of the resistances is obtained bysimulating the circuit under all operating conditions using computeraided design software.

[0108] As shown in eq. (2) a small value of R₃ reduces t₁ while a smallvalue of R₂ reduces t₂; a small ratio $\frac{R_{3}}{R_{2}}$

[0109] reduces the voltage decay of V_(CIN)(t). The total time t₁+t₂ canbe minimized through the choice of R₁, R₂ and I_(Q) as shown in eqs.(2), (3) and (4). Reducing C_(L), the load on node Q, also reduces t₂through reduction of C′.

[0110] As the above discussion shows, correct circuit operation isensured by regulation of the ratio $\frac{R_{3}}{R_{2}},$

[0111] which is the ratio of the equivalent resistances of transmissiongates TG3 and TG2. The preferred embodiment of critical race controltherefore controls critical races through the calculated regulation oftransistor resistances in the transmission gates.

[0112] It will be readily apparent to persons skilled in the art thatthere exist many variations on how to implement the delay in the varioussections of the loop. For example the slower of the two transmissiongates, TG2 in FIG. 2, can be replaced by two weak transistors that are“ON” all the time. The transistors act like large resistive valueresistors. Alternatively a large passive resistor can replace the twotransistors to reduce contacts and connections. These implementationslighten the current load required from the clock source and itscomplement. Alternatively the inverter and the transmission gate can beintegrated together to form a switched inverter with all the variationsavailable as shown in the literature.

[0113] It will also be readily apparent to persons skilled in the artthat the critical race control principle can also be applied to othercircuits such as multi-loop circuits where some paths share more thantwo loops. In such cases the delay in a loop section might be needed tobe low when embedded in one loop and high when embedded in another loop.

[0114] Critical race control can also be implemented in circuits wheresingle pass transistors are used in preference to transmission gates.The modification of the delay is obtained by changing the dimensions ofthe appropriate pass transistors.

[0115] However due to its innovative principle of inserting a relativedelay in digital circuits, critical race control can also be used todevelop new kind of integrated circuits and applications resulting incircuits with smaller silicon area and lower power dissipation.

[0116] The following are some examples of new circuits or improvementsto existing ones when using the critical race control technique. FIG.5a-c shows how reduction in the number of gates enabled by critical racecontrol can be further applied to substantially lower both the powerdissipation and the number of gates, therefore the silicon area,required to implement registers on a chip. The technique used toeliminate gate G2 in FIG. 1 can also be used to eliminate gate G4 whenthe flip-flop is followed by another flip-flop as occurs in shiftregisters, counters and other circuits.

[0117]FIG. 5a shows two stages 10, 20 of a static shift register asdelimited by the heavy broken line. Inverter G4 of the left stage 10(flip-flop, with output Q1) that appears in FIG. 1 has been eliminated.The input to gate TG4 is now provided by the output of inverter G1 ofthe following stage (right flip-flop with output Q2). This creates theloop: TG4, G3 (left stage), TG1, G1 (right stage). The control of thecritical races in this loop is done as described above. By increasingthe delay of gate TG4 with respect to the delay of gate TG1 (of thefollowing stage) the signal coming from Q1 will toggle gate G1 beforethe old signal at the output of G1 has the opportunity to (wrongly)toggle gate G3 of the left flip-flop. This difference in delays willensure correct operation of the circuit.

[0118] The resulting stage consists now of four transmission gates: TG1,TG2, TG3 and TG4 and of two gates only: G1 and G3. It requires thereforeless silicon area for implementation. As the number of gates in whichtransistors are connected between the power supply and ground isminimized, this stage also consumes less power.

[0119] Thus in all stages of the shift register, except the final one,the critical race conditions are controlled by the ratio of theresistances of transmission gates TG3 and TG2 in the same stage, andthat of transmission gate TG4 with that of transmission gate TG1 in thefollowing stage. The final stage of the example shown in FIG. 5a isconfigured as the flip-flop shown in FIG. 2.

[0120]FIG. 5b compares the output waveforms from each stage of two3-stage shift registers. The upper panel 50 output waveforms belong tothe shift register implemented with conventional D flip-flops while thelower panel 60 output waveforms belong to the shift register using CRC Dflip-flops as shown in FIG. 5a. The similarity between the waveformsdemonstrate that the CRC D flip-flop has speed and delay characteristicsalmost identical to those of the conventional D flip-flop.

[0121]FIG. 5c shows the integration of the current waveforms, resultingin the average power dissipation, of the two kinds of flip-flops overone period of the clock according to: [3] Sung Mo Kang, “AccurateSimulation of Power Dissipation in VLSI Circuits”, IEEE Journal ofSolid-State Circuits, Vol. SC-21, No. 5, October 1986, pp. 889-891.

[0122] The ordinate in FIG. 5c represents micro-watts. The first trace110 represents the average power dissipation per clock period of theconventional D flip-flop that reaches a maximum of about 670 micro-wattsduring one clock period. The average power dissipation of the CRC Dflip-flop under the exact same conditions, represented by the secondtrace 120, reaches a level of about 520 micro-watts thus demonstratingthe lower power dissipation of the CRC D flip-flop as compared to aconventional one.

[0123] Additionally, it will be noted that inverting the ratio ofresistances of TG2 to TG3 and of TG1 to TG4 in FIG. 5a causes the sameshift register circuit to shift data in the reverse direction whileoperating with the same clock. This operation in the reverse directionwithout the need of a reverse clock signal is obtain due to the propertyof the critical race control technique which allows us to specify whichof the two inputs will be the final value latched in the loop. One inputto the loop is the conventional output of the previous stage. The secondinput available in the CRC flip-flop is the one coming from the nextstage.

[0124] The invention embodies therefore two basic elements: one elementis a loop that is divided into two or more sections and allows thereforetwo or more inputs respectively to be inputs to the loop. The secondelement is the control of the delay of each section by sizing theelements of its transmission gate and by sizing the currents of theinverters in the loop. In the present examples, when the loop is dividedinto two sections and allows two inputs, the loop exhibitsbidirectionality, which is the capability of latching the value eitherfrom its left input or from its right input.

[0125] A shift left/shift right register is shown in FIG. 6a where twotransmission gates labeled TG2B and TG4B, and two transistors labeled T2and T4 are added in each latch to provide the ratio of delays needed toshift the data in the reverse direction.

[0126] The representative waveforms 200, 210, 220, 230, 240, 250 areillustrated in FIG. 6b. The uppermost waveform 200 is the B/F Controlsignal showing the Shift Right and Shift Left. The next waveform 210 isthe Input signal, followed by the Clock 220. The next three waveformsare the outputs of the first stage 230, second stage 240 and third stage250.

[0127] A control signal, labeled BW, controls the desired forward andbackward data shifting directions by enabling transistors T2 and T4.When the forward direction is desired, the signal BW=0 and transistorsT2 and T4 are off. Transmission gates TG2B and TG4B are disconnected andthe CRC circuit reverts to its forward data shifting function accordingto the correct sizing of transmission gates TG2 vs. TG3 and TG4 vs. TG1of the following stage as shown in FIG. 5a.

[0128] When the backward data shifting direction is desired, the controlsignal BW=1. This activates transistors T2 and T4 and connectstransmission gates TG2B and TG4B in parallel to transmission gates TG2and TG4 respectively. Transmission gates TG2B and TG4B are sized sothat, together with transmission gates TG2 and TG4 respectively inparallel, they have smaller transmission delays than transmission gatesTG3 and TG1 (of the next stage) respectively.

[0129] When CLK is low, in each stage of the shift register transmissiongates TG4, TG4B and TG1—belonging to the stage on the right—are open(on) and transmission gates TG3, TG2 and TG2B are closed (off). Theupper loop in each stage, comprising TG4 in parallel with TG4B, G3 andTG1 and G1 from the stage on its right, is closed and the lower loopconsisting of G1, TG3 G3 and TG2, is meanwhile open.

[0130] The upper closed loops supply different voltages at the terminalsof transmission gates TG2 and TG3. Node Q1, through TG1, applies avoltage at one terminal of TG2 in parallel with TG2B while node Q2 (nextstage) supplies a different voltage at the second terminal of TG2 inparallel with TG2B. Similarly, the voltages at each terminal of TG3 comefrom the closed loops from different stages.

[0131] Transmission gate TG2B, in parallel with TG2, is sized to have asmaller delay than transmission gate TG3. Thus when CLK goes high, andCLKB goes low, the value of Q2 will be the preferred value latched inthe loop consisting of G1, TG3, G3 and TG2B in parallel with TG2. Thusthe value that was previously in the upper loop now appears in the lowerloop at its left. Similarly, transmission gate TG4B, in parallel withTG4, is sized to have a smaller delay than transmission gate TG1. Thuswhen CLK goes high, and CLKB goes high, the value at the output of G1will be latched in the closed loop consisting of TG1, G1, TG4B inparallel with TG4 in preference to the value on node Q1. Therefore thevalue that was in the previous lower closed loop now appears in theupper loop on its left. These operations are done in all stages of theshift register synchronously.

[0132] This circuit has no equivalent in present integrated circuits asthose require an additional clock signal to shift data in the reversedirection. The proposed CRC circuit uses only one clock signal forshifting data left or right and is an example of the capabilities of theCRC method.

[0133] It will be readily apparent to persons skilled in the art thatthe loops can be implemented with more than two sections and that thisconfiguration can then be extended to comprise multi-loops, not justleft and right ones.

[0134] The CRC method can also be exploited in all the common circuitvariations used for implementation of D flip-flops. FIG. 7 shows theembodiment of the CRC D flip-flop operating with a single clock phase,also called “True Single Phase Clock” (TSPC). The transmission gates arereplaced by single pass-transistors. Thus transistors T1, T2, T3 and T4in FIG. 7 replace transmission gates TG1, TG2, TG3 and TG4 respectivelyin FIG. 2. A weak n-type transistors T5, fed from the output of G1, hasbeen added to act as pull-down at the input of gate G1. This transistoreliminates the Vth loss associated with the p-type single passtransistor T1. Similarly the weak p-type transistor T6 at the input ofG3 acts as pull-up to eliminate the Vth loss associated with the singlepass transistor T3. When operating in a shift register gate G4 can befurther eliminated by feeding T4 from the output of gate G1 in thefollowing stage similarly to the operation of the shift register stagesshown in FIG. 5. When G4 is eliminated and G3 is replaced by an invertera shift register stage can be implemented with 10 transistors only

[0135] Critical Race Control can also be used to reduce the silicon arearequired for implementation and to lower the power dissipation ofconventional circuits such as static double edged- triggered Dflip-flops (DETDFF). DETDFF's move data at each clock transition (low tohigh and high to low), which doubles the data throughput at a givenclock speed or, alternatively, halves the clock speed necessary for agiven data flow obtaining thus substantial reduction in powerdissipation. However, conventional techniques of constructing staticdouble-edged flip-flops require a large numbers of components andresults in relatively large circuit size and power consumption.Accordingly, the circuits have not been an attractive alternative foraddressing the circuit data throughput and speed objectives discussedabove.

[0136] A typical static DETDFF is shown in FIG. 8 (See K. Y. Yun et. al.“High-performance two phase micropipeline building blocks: doubleedge-triggered latches and burst-mode select and toggle circuits”, IEEProc.-Circuits Devices Syst., Vol. 143, No. 5, October 1996,pp.282-288). This device is essentially a pair of static truesingle-phase master-slave flip-flop circuits configured in parallel,such that one flip-flop responds to the clock going high and the secondflip-flop responds to the clock going low. The outputs of bothflip-flops are then summed to a common output.

[0137]FIG. 9a shows an embodiment of a static DETDFF constructedaccording to the critical race control technique. This circuit usesfewer components than a similar circuit of conventional design, andtherefore it requires less silicon area for implementation. In FIG. 9agate G3 is shared by the upper loop comprising gates G1, TG2, G3, TG3,and by the lower loop comprising gates G2, TG5, G3 and TG6. When theclock is low, transmission gates TG2, TG3, and TG4 are open, andtransmission gates TG1, TG5, and TG6 are closed. The upper loop is nowlatched and determines the output of the DETDFF. During that period thenew data appears trough transmission gate TG4 at the output of Gate G2.When the clock goes high, all transmission gates switch to theircomplementary states. The lower loop is now latched and determines theoutput of the DETDFF.

[0138] The critical race control technique is applied in each loop toprevent the critical race arising between the new incoming data and theprevious data. For example when the clock goes high the new valueappearing (inverted) at the output of G2 has to compete—ifdifferent—with the data latched at the previous clock transition andappearing at the output of G3 in the (lower) loop consisting of G2, T5,G3 and T6. For correct operation the new data appearing inverted at theoutput of G2 should prevail. According to the critical race controltechnique the data path from the output node of G3 to the input node ofG2 should have longer propagation delay than the path from the outputnode of G2 to the input node of G3. Therefore transmission gate T6 isdesigned to have a larger delay than transmission gate T5. T6 isaccordingly labeled with an asterisk. Similarly in the upper loop,transmission gate T3, also labeled with an asterisk, has a delay largerthan transmission gate T2 to control the critical race in that loop.

[0139]FIG. 9b shows the waveforms 300, 310, 320, 330, 340 resulting fromthe simulation of a shift register using double edge-triggered Dflip-flops implemented according to the CRC architecture. The uppertrace 300 represents the input signal. The second trace from the top 310shows the clock waveform. The last three waveforms show the output ofthe first 320, second 330 and third stage 340 of the shift registerrespectively. As can be seen the circuits respond to each transition ofthe clock. It should be clear to those skilled in the art that differentembodiments of the circuit shown in FIG. 9a are possible.

[0140] It is readily apparent that this new architecture, using criticalrace control, can easily be used for the realization of T and J-K doubleedge-triggered master/slave flip-flops as the various types offlip-flops differ only by the type of combinational circuits connectedat their input nodes.

[0141] The technique of critical race control as applied to synchronoussequential circuits can also be applied to asynchronous sequentialcircuits. The application of critical race control to asynchronouscircuits is particularly relevant as up to the present the primaryobjective of asynchronous networks consisted in choosing a stateassignment that prevented critical races while simplification of thelogic was relegated to secondary considerations. Using the critical racecontrol technique can therefore lead to a reduced number of logic gatesneeded to implement asynchronous circuits, and to a reduction in powerdissipation, without further concern about critical races as they caneasily be controlled.

[0142] The basic sequential element in asynchronous circuits is theSet-Reset (S-R) latch. The S-R latch stores 1 bit of information andconsists of two cross-coupled NAND or NOR gates with two inputs labeledS and R and two output nodes labeled Q and Q′, where node Q′ indicatesthe complement of Q. Implementation of the S-R latch with NOR gates andwith NAND gates are shown in FIGS. 10a and 10 b respectively.

[0143] In S-R latches implemented with 2 NOR gates in a cross-coupledcircuit, a positive voltage level applied at input S sets node Q′ to aLOW logic value after some delay and consequently output Q to a HIGHlogic value after an additional delay. The latch stays in this stateuntil a positive voltage level applied to input R resets the state ofthe latch to Q=0 after some delay and consequently Q′=1 after additionaldelay. According to present circuit implementations inputs S and R cannever be applied simultaneously as the final state of the latch cannoteasily be determined in this case. The final state of the S-R latch willbe determined by which of the input nodes, set or reset, will be thelast one to undergo a falling edge.

[0144] In S-R latches implemented with 2 cross-coupled NAND gates, anegative voltage level applied at input S sets the output Q to a HIGHlogic value after some delay and consequently node Q′ to a LOW logicvalue after additional delay. Note that the location of the Q and Q′outputs in relation to the inputs, and therefore their delays, aredifferent from those of the NOR-implemented latch. The latch stays inthis state until a negative voltage level applied to input R resets thestate of the latch to Q′=1 after some delay and consequently node Q=0after additional delay. Similarly to the NOR-implemented latch, inputs Sand R can never have inputs applied simultaneously.

[0145] The application of critical race control to an asynchronouscircuit can be demonstrated using the following example. FIG. 11 showsan asynchronous sequential circuit with critical races. The circuitconsists of two NAND-implemented S-R latches with combinational circuitsat the Set and Reset nodes of each of the two latches.

[0146] The operation of the circuit is the following: when the externalinput X is 0 (Xb=1) and with internal state Q1Q2=00 (Q1 bQ2 b=11), thenS1, R1 and S2=1, while R2=0. This initial state is thus stable as theinput, X=0 does not cause changes in Q1 and Q2.

[0147] Critical races occur when X=1 (Xb=0). At that instant a negativepulse appears at both S1 and S2 nodes while node R1 remains at 1 andnode R2 reverts from 0 to 1. When the two latches are thus in the setstate both Q1 and Q2 should rise to 1. The final state of the circuitdepends on which of nodes Q1 b or Q2 b (and therefore also Q1 and Q2)switches first. If, due to lower parasitic capacitances at the S1 nodeand lower loading at the Q1 and Q1 b outputs, the first latch is set(Q1=1, Q1 b=0) before the second latch, the circuit will reach thestable state in which X=1 and Q1=1 and Q2=0. If, on the other hand, thesecond latch is set first (Q2=1, Q2 b=0), the circuit will reach theequally stable state in which X=1 and Q1=0 and Q2=1. A third stablestate is also possible if the latches in the circuit behave identically.If both Q1 and Q2 switch to 1 simultaneously (Q1 b=Q2 b=0), the circuitwill remain in this stable state as S1=R1=S2=R2=1.

[0148] Using the critical race control technique the final state of thecircuit can be unambiguously determined by controlling the delays in thevarious parts of the loop. The redrawn circuit is shown in FIG. 12. Twomain loops are present in the circuit. The first loop consists of gateG1, driving node S1, through Latch1 to output Q1 b, to gate G2 drivingnode S2, through output Q2 b of Latch2 and back to gate G1. The secondloop consists of gate G3 driving node R1 through the output Q1 b ofLatch1 to gate G4 driving node R2, through Latch2 to the output Q2 andback to gate G3.

[0149] Thus, if the delay beginning from input X at gate G1 to outputnode Q1 b of Latch1 is smaller than the delay from input X at gate G2 tonode S2 of Latch2, Latch1 will be set before Latch2 and the first finalstate described herein will be established. In the reverse case, thesecond final state will be established. If the delays are exactlyidentical, the third stable state will be established.

[0150] The increase in delay of one part of the loop versus the othercan be concentrated in more than one gate. Thus delaying the setting ofthe second latch with respect to that of the first latch is obtained byincluding none, part or all of the delay in the latches themselves.

[0151] It should be readily apparent to the person skilled in the artthat the critical race control method can be applied to insure thatsimultaneous application of both set and reset pulses will yieldunambiguous result when maximum pulse width is known. In that case, themaximum time of occurrence of the trailing edge of either the set orreset pulse can be calculated and taken into consideration whendesigning the difference of delays of the sections of the loop.

[0152] Gate delay modification can be obtained by modifying the sizes oftwo transistors in a transmission gate and/or modifying the size of thetransistors in the latches. Two input logic gates such as OR, AND, NORand NAND can be implemented using transmission gates for ease of delaymodification as shown in FIG. 13 for NAND and NOR logic functions.Modifying the sizes of four transistors in a standard logic gate isfeasible but more cumbersome if proper switching threshold value has tobe retained.

[0153] It should be readily apparent from the examples described abovethat the critical race control technique is effective in controllingcritical races in multi-loop circuits by choosing adequate resistanceratios to accommodate the delays between various loops. The delaydifference between the various parts of the loop is obtained bymodifying the transistor sizes in the transmission gates. While this isthe preferred method, other means are also available such as modifyingthe size of the transistors in the logic gates, modifying parasiticcapacitances, modifying the threshold of the transistors or any othertechnique presently available. The delay ratio can also be implementedusing the wide range of techniques presently in use such as single passtransistors, single polarity clock signal and transistor and gatethreshold modification.

[0154] Also, alternate means exist for regulating the relative delays.For example, a transistor in the path of a critical race might berobustly configured as a high/low switch or gate shunt, being responsiveto selective control. Therefore, the “ideal” regulation values fordelays and resistance ratios between gates in a particular applicationare best determined experimentally for the particular application.

[0155] The critical race control innovation can be used to develop newintegrated circuits that have at present no integrated equivalent.Alternatively, it can be implemented as a retrofit to improve existingsystems.

[0156] It is readily apparent that the critical race control techniquecan be used in synchronous and asynchronous circuits with any of themethods for implementing the delays and is not limited to theembodiments presented herein. Various variations and modifications maybe made without departing from the scope of the present invention

[0157] Numerous characteristics and advantages have been set forth inthe foregoing description, together with details of structures andfunctions of critical race control, and the novel features thereof arepointed out in appended claims. The disclosure, however, is illustrativeonly, and changes may be made in arrangement and details, within theprinciple of the invention, to the full extent indicated by the broadgeneral meaning of the terms in which the appended claims are expressed.

[0158] The objects and advantages of the invention may be furtherrealized and attained by means of the instrumentalities and combinationsparticularly pointed out in the appended claims. Accordingly, thedrawing and description are to be regarded as illustrative in nature,and not as restrictive.

What is claimed is:
 1. A method for producing efficient integratedsequential circuits, comprising the steps of: providing at least onedata input signal and at least one clock signal; designing one or morecircuit loops each having a plurality of sections and two or moreswitches wherein said switches in said loops separate between saidsections; and controlling a critical race of said loops by adjusting arelative delay of said sections.
 2. The method for producing efficientintegrated sequential circuits according to claim 1, wherein saidswitches are one or more transistors and said relative delay isregulated by adjusting transistor dimensions.
 3. The method forproducing efficient integrated sequential circuits according to claim 1,wherein said switches are one or more transistors and said relativedelay is regulated by adjusting a resistance of said transistors.
 4. Themethod for producing efficient integrated sequential circuits accordingto claim 1, wherein said switches are one or more transistors and saidrelative delay is regulated by adjusting a capacitance of saidtransistors.
 5. The method for producing efficient integrated sequentialcircuits according to claim 1, wherein said switches are one or moretransmission gates and said relative delay is regulated by adjusting aresistance/capacitance (RC) time constant of said transmission gates. 6.The method for producing efficient integrated sequential circuitsaccording to claim 1, wherein said relative delay is adjustable byexternal parameters.
 7. The method for producing efficient integratedsequential circuits according to claim 6, wherein said externalparameters include clock frequencies, supply voltages (Vdd), groundsupplies (Vss), bias voltages, and temperature.
 8. The method forproducing efficient integrated sequential circuits according to claim 6,wherein said relative delay is dynamically controllable by said externalparameters.
 9. The method for producing efficient integrated sequentialcircuits according to claim 1, wherein said switches are transmissiongates and said relative delay is regulated by adjusting a set offabrication process parameters affecting said transmission gates. 10.The method for producing efficient integrated sequential circuitsaccording to claim 9, wherein said fabrication process parametersinclude doping concentration, implant concentration, threshold voltage,polysilicon dimensions, polysilicon composition, diffusion dimensions,metal dimensions, substrate dimensions, and oxide dimensions.
 11. Themethod for producing efficient integrated sequential circuits accordingto claim 1, wherein said switches are one or more transistors andfurther comprising the step of locating said transistors in closeproximity.
 12. The method for producing efficient integrated sequentialcircuits according to claim 1, wherein said relative delay is a firstpropagation delay in a first section as compared to a second propagationdelay in a second section, wherein said first and second section arewithin one of said loops.
 13. The method for producing efficientintegrated sequential circuits according to claim 1, wherein saidrelative delay is a first propagation delay in a first section ascompared to a second propagation delay in a second section, wherein saidfirst and second sections are coupled.
 14. The method for producingefficient integrated sequential circuits according to claim 1, whereinsaid relative delay is introduced by resistors.
 15. The method forproducing efficient integrated sequential circuits according to claim 1,further comprising logic circuits in said sections, and wherein saidlogic circuits provide said relative delay.
 16. The method for producingefficient integrated sequential circuits according to claim 1, whereinsaid integrated circuits are from the group comprising singleedge-triggered flip-flops, double edge-triggered flip-flops, Dflip-flops, T flip-flops, J-K flip-flops, S-R flip-flops, or binarymemory circuit.
 17. The method for producing efficient integratedsequential circuits according to claim 1, wherein a data flow is in atwo or more directions.
 18. A sequential circuit comprising; a datainput; a data output; a loop with a plurality of sections coupled tosaid data input and said data output; and a means for controlling acritical race by adjusting a relative time delay between said pluralityof sections.
 19. The sequential circuit according to claim 18, whereinsaid means for controlling is changing a ratio of aresistance/capacitance (RC) time constant between said sections.
 20. Thesequential circuit according to claim 18, further comprising two or moretransmission gates and a plurality of logic devices connected in saidloop and wherein said relative time delay is a difference in propagationtime delay between said sections of said loop.
 21. The sequentialcircuit according to claim 18, wherein said means for controlling is aratio of resistance of said sections of said loop.
 22. The sequentialcircuit according to claim 21, wherein said ratio of resistance is ofsaid transmission gates of said sections.
 23. The sequential circuitaccording to claim 20, wherein said relative delay is between said logicdevices of said sections.
 24. The sequential circuit according to claim20, wherein said relative time difference is changed by adjusting a sizeof said transmission gates.
 25. The sequential circuit according toclaim 18, wherein said relative time difference is changed by adjustinga size of capacitance of said sections.
 26. A sequential circuitcomprising; a data input; a first loop with a plurality of first loopsections, wherein said first loop is coupled to said data input; asecond loop with a plurality of second loop sections, wherein saidsecond loop is coupled to said first loop; an output node coupled tosaid circuit; and a means for controlling a critical race between saidfirst loop sections and between said second loop sections.
 27. Thesequential circuit according to claim 26, wherein said means forcontrolling is changing a relative time delay in said first loopsections.
 28. The sequential circuit according to claim 26, wherein saidmeans for controlling is changing a relative time delay in said secondloop sections.
 29. The sequential circuit according to claim 26, whereinsaid means for controlling is changing a relative time delay in saidfirst loop sections coupled to said second loop sections.
 30. Thesequential circuit according to claim 26, wherein said means forcontrolling is changing a ratio of an resistance/capacitance (RC) timeconstant between said first loop sections and said second loop sections.31. The sequential circuit according to claim 26, further comprising twoor more transmission gates and a plurality of logic devices connected insaid first loop and comprising two or more transmission gates and aplurality of logic devices connected in said second loop, and whereinsaid relative time delay is a difference in propagation time delaybetween said sections of said first loop and said sections of saidsecond loop.
 32. The sequential circuit according to claim 28, whereinsaid means for controlling is a ratio of resistance of said sections ofsaid first loop and said sections of said second loop.
 33. Thesequential circuit according to claim 29, wherein said ratio ofresistance is between said transmission gates of said sections of saidfirst loop and said transmission gates of said sections of said secondloop.
 34. The sequential circuit according to claim 29, wherein saidrelative delay is between said logic devices of said sections of saidfirst loop and said logic devices of said sections of said second loop.35. The sequential circuit according to claim 28, wherein said relativetime difference is changed by adjusting a size of said transmissiongates.
 36. The sequential circuit according to claim 26, wherein saidrelative time difference is changed by adjusting a size of capacitancesof said sections of said first loop and said sections of said secondloop.